1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor memory device. More particularly, the present invention relates to a method for manufacturing a capping layer covering a metal-insulating-metal (MI M) capacitor.
2. Description of the Related Art
As semiconductor devices become more highly integrated, individual devices occupy less volume in the chip. Capacitors, which store information in a dynamic random access memory (DRAM) device, however, must still have a capacitance at least as high as older, larger capacitors. Accordingly, there have been several suggestions to provide capacitors having sufficient capacitance. A first suggestion is to form capacitors with three-dimensional lower electrodes, such as a cylinder or a fin type. A second suggestion is to cover the surface of the lower electrode with hemispherical grains to increase a surface area thereof. A third suggestion is to reduce a thickness of the dielectric layer. A fourth suggestion is to use a dielectric layer having a high dielectric constant or a ferroelectric layer as a dielectric layer of capacitor.
However, the methods for increasing the volume of the lower electrode and decreasing the thickness of the dielectric layer have almost reached their limits. Currently, capacitance is increased using a dielectric layer having a high dielectric constant or a ferroelectric layer.
Conventionally, Ta2O5 or BST((Ba, Sr)TiO3) is used as the dielectric layer having a high electric constant or a ferroelectric layer. Conduction materials, which do not react to the dielectric layer having a high dielectric layer or a ferroelectric layer and have a high work function, such as platinum (Pt), ruthenium (Ru), iridium (Ir), rhodium (Rh), or osmium (Os), are used for the capacitor electrode. However, a high dielectric layer requires a crystallization process after being deposited, and then a thermal process to cure internal defects, even after forming the capacitor. This necessitates a complicated manufacturing process.
Accordingly, a conventional solution is to form a capping layer on the capacitor to crystallize the dielectric layer and cure defects of the dielectric layer with a single thermal process. In this method, a capacitor including a lower electrode, a dielectric layer having a high dielectric constant and an upper electrode is formed on the semiconductor substrate. Next, a capping layer is formed to cover the capacitor. The capping layer may be a TaOx layer. Referring to FIG. 1, the capping layer is formed by stabilizing for deposition in an oxygen gas atmosphere (A), depositing a TaOx layer by providing a TaO source and oxygen gas (B), and performing a purge process (C) without providing oxygen gas. By a thermal process of the capping layer deposited as above at a selected temperature, the dielectric layer having a high dielectric constant is crystallized and cured of defects, while also crystallizing the capping layer. This avoids the need for multiple thermal processes.
However, as described above, since stabilizing for deposition and depositing the capping layer are performed in an oxygen ambient, oxygen diffuses into the upper electrode beneath the capping layer. Oxygen provided during deposition is used up in creating the TaOx capping layer, but most of the oxygen provided in the deposition stabilizing step diffuses into the upper electrode.
Accordingly, the oxygen content in the upper electrode is increased, a high resistance by-product such as TiO may be generated at the interface between the upper electrode and a barrier metal layer (Ti/TiN) of a metal interconnection layer, when the upper electrode is connected to the metal interconnection layer having the barrier metal such as Ti/TiN. At that time, the high resistance by-product, such as TiO, increases contact resistance.